A comprehensive methodology to determine optimal coherence interfaces for many-accelerator SoCs

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dc.creatorBhardwaj, Kshitij
dc.creatorHavasi, Marton
dc.creatorYao, Yuan
dc.creatorBrooks, David M
dc.creatorHernández-Lobato, José Miguel
dc.creatorWei, Gu-Yeon
dc.date2021-05-24T13:46:14Z
dc.date2021-05-24T13:46:14Z
dc.date2020-08-10
dc.date.accessioned2026-08-03T02:05:44Z
dc.descriptionModern systems-on-chip (SoCs) include not only general-purpose CPUs but also specialized hardware accelerators. Typically, there are three coherence model choices to integrate an accelerator with the memory hierarchy: no coherence, coherent with the last-level cache (LLC), and private cache based full coherence. However, there has been very limited research on finding which coherence models are optimal for the accelerators of a complex many-accelerator SoC. This paper focuses on determining a cost-aware coherence interface for an SoC and its target application: find the best coherence models for the accelerators that optimize their power and performance, considering both workload characteristics and system-level contention. A novel comprehensive methodology is proposed that uses Bayesian optimization to efficiently find the cost-aware coherence interfaces for SoCs that are modeled using the gem5-Aladdin architectural simulator. For a complete analysis, gem5-Aladdin is extended to support LLC coherence in addition to already-supported no coherence and full coherence. For a heterogeneous SoC targeting applications with varying amount of accelerator-level parallelism, the proposed framework rapidly finds cost-aware coherence interfaces that show significant performance and power benefits over the other commonly-used coherence interfaces.
dc.formatapplication/pdf
dc.identifier9781450370530
dc.identifier2153-1633
dc.identifierhttps://www.repository.cam.ac.uk/handle/1810/322875
dc.identifier10.17863/CAM.70329
dc.identifier.urihttps://repo.dare.co.zw/handle/123456789/163508
dc.languageeng
dc.publisherAssociation for Computing Machinery (ACM)
dc.publisherhttps://doi.org/10.1145/3370748.3406564
dc.rightsAll rights reserved
dc.subject33 Built Environment and Design
dc.subject40 Engineering
dc.subject4008 Electrical Engineering
dc.subject4009 Electronics, Sensors and Digital Hardware
dc.subject3301 Architecture
dc.subject7 Affordable and Clean Energy
dc.titleA comprehensive methodology to determine optimal coherence interfaces for many-accelerator SoCs
dc.typeConference Object

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